US 12,332,837 B2
Sorting the nodes of an operation unit graph for implementation in a reconfigurable processor
Hong Suh, Palo Alto, CA (US); and Sumti Jairath, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Jul. 25, 2023, as Appl. No. 18/225,856.
Claims priority of provisional application 63/392,364, filed on Jul. 26, 2022.
Claims priority of provisional application 63/392,374, filed on Jul. 26, 2022.
Claims priority of provisional application 63/392,368, filed on Jul. 26, 2022.
Prior Publication US 2024/0037061 A1, Feb. 1, 2024
Int. Cl. G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/78 (2006.01)
CPC G06F 15/80 (2013.01) [G06F 9/30036 (2013.01); G06F 9/3836 (2013.01); G06F 15/7871 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a compiler that is executable in one or more processors coupled to a storage medium comprising:
receiving an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes;
determining a first position of an ordered sequence of nodes as a current position of the ordered sequence of nodes;
repeating as long as the set of unsorted nodes comprises at least one unsorted node:
determining, from the set of unsorted nodes, a node-to-be-sorted in the operation unit graph;
adding the node-to-be-sorted to an ordered data structure; and
repeating until the ordered data structure is empty:
in order of the ordered data structure, removing a next node-to-be-sorted from the ordered data structure,
inserting the next node-to-be-sorted as the currently inserted node at the current position of the ordered sequence of nodes,
assigning a subsequent position of the ordered sequence of nodes as the current position of the ordered sequence of nodes,
determining neighboring nodes of the currently inserted node from the set of unsorted nodes, wherein each one of the neighboring nodes is separated from the currently inserted node by one of the edges,
adding each one of the neighboring nodes as a node-to-be-sorted to the ordered data structure, and
removing the currently inserted node from the set of unsorted nodes;
receiving a hardware description describing a reconfigurable processor having interconnects, physical compute units and/or physical memory units;
using the hardware description to determine an assignment of the edges and nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units of the reconfigurable processor during placement and routing of the operation unit graph; and
generating a configuration file that is adapted for being applied to the reconfigurable processor for configuring the reconfigurable processor with the assignment of the edges and the nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units.