US 12,332,828 B2
Graph acceleration solution with cloud FPGA
Shuangchen Li, Sunnyvale, CA (US); Dimin Niu, Sunnyvale, CA (US); Hongzhong Zheng, Los Gatos, CA (US); Zhe Zhang, Beijing (CN); and Yuhao Wang, Sunnyvale, CA (US)
Assigned to Alibaba (China) Co., Ltd., Hangzhou (CN)
Filed by Alibaba (China) Co., Ltd., Hangzhou (CN)
Filed on Nov. 30, 2022, as Appl. No. 18/072,062.
Claims priority of application No. 202210774994.7 (CN), filed on Jul. 1, 2022.
Prior Publication US 2024/0004824 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01); G06F 3/06 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a host comprising a host memory;
one or more processors; and
a circuitry board,
wherein:
the circuitry board is communicatively coupled with the host via a first peripheral component interconnect express (PCIe) connection, the circuitry board comprising:
an access engine circuitry configured to:
fetch a portion of structure data of a graph from a pinned memory in the host memory via the first PCIe connection;
perform node sampling using the fetched portion of the structure data to select one or more sampled nodes of the graph;
fetch a portion of attribute data of the graph from the pinned memory via the PCIe first connection according to the selected one or more sampled nodes; and
send the fetched portion of the attribute data of the graph to the one or more processors, and
the one or more processors are configured to perform graph neural network (GNN) processing for the graph using the portion of the attribute data of the graph.