US 12,332,826 B2
Die-to-die interconnect
Debendra Das Sharma, Saratoga, CA (US); Swadesh Choudhary, Mountain View, CA (US); Narasimha Lanka, Dublin, CA (US); Lakshmipriya Seshan, Sunnyvale, CA (US); Gerald Pasdast, San Jose, CA (US); and Zuoguo Wu, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 29, 2022, as Appl. No. 17/852,865.
Claims priority of provisional application 63/295,218, filed on Dec. 30, 2021.
Prior Publication US 2022/0342840 A1, Oct. 27, 2022
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a port to couple to another die over a die-to-die (D2D) link, wherein the port comprises:
physical layer (PHY) circuitry comprising:
a logical PHY;
a first number of sideband lane pins, wherein the sideband lane pins are to carry data for use in training and management of the D2D link; and
a second number of mainband lane pins, wherein the mainband lane pins are to implement a main data path of the D2D link, and the second number of mainband lane pins comprise forwarded clock, a valid lane pin, and a plurality of data lane pins,
wherein the logical PHY coordinates functions of the sideband lane pins and the mainband lane pins.