US 12,332,824 B2
Backside interface for chiplet architecture mixing
Gabriel Hsiuwei Loh, Bellevue, WA (US); and Todd David Basso, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 28, 2022, as Appl. No. 18/090,254.
Prior Publication US 2024/0220438 A1, Jul. 4, 2024
Int. Cl. G06F 13/40 (2006.01); G06F 1/08 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC G06F 13/4068 (2013.01) [G06F 1/08 (2013.01); H01L 23/538 (2013.01); H01L 25/0655 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a substrate;
a first chiplet area for receiving a first chiplet on the substrate;
a second chiplet area for receiving a second chiplet on the substrate;
a host die on the substrate directly coupled to the first chiplet area via a first plurality of conductive routes, wherein the host die is configured to route off-chip communication for the first chiplet; and
a backside interconnect comprising a second plurality of conductive routes that extend through the substrate and are separate from the first plurality of conductive routes, wherein the second plurality of conductive routes are directly coupled between the first chiplet area and the second chiplet area and configured to bypass the host die for direct inter-chiplet communication between the first chiplet and the second chiplet.