US 12,332,823 B2
Parallel dataflow routing scheme systems and methods
Liang Han, Campbell, CA (US); ChengYuan Wu, Fremont, CA (US); Guoyu Zhu, San Jose, CA (US); Yang Jiao, San Jose, CA (US); Rong Zhong, Fremont, CA (US); and Yunxiao Zou, Shanghai (CN)
Assigned to T-Head (Shanghai) Semiconductor Co., Ltd., Shanghai Free Trade Area (CN)
Filed by T-Head (Shanghai) Semiconductor Co., Ltd., Shanghai Free Trade Area (CN)
Filed on May 25, 2022, as Appl. No. 17/824,824.
Prior Publication US 2023/0244626 A1, Aug. 3, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06F 15/173 (2006.01)
CPC G06F 13/4068 (2013.01) [G06F 15/17312 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of parallel processing units (PPUs) included in a first chip, each of the PPUs includes:
a plurality of processing cores;
a plurality of memories, wherein a first set of the memories couple to a first set of the plurality of processing cores; and
a plurality of interconnects in an inter-chip network (ICN) configured to communicatively couple the plurality of PPUs,
wherein each of the PPUs is configured to communicate over the ICN in accordance with respective routing tables that are stored and reside in registers included in the respective PPUs, and wherein the respective routing tables include indications of minimum links available to forward a communication from the PPU to another PPU.