US 12,332,813 B2
Non-posted write transactions for a computer bus
Rajesh M. Sankaran, Portland, OR (US); David J. Harriman, Portland, OR (US); Sean O. Stalley, Hillsboro, OR (US); Rupin H. Vakharwala, Hillsboro, OR (US); Ishwar Agarwal, Portland, OR (US); Pratik M. Marolia, Hillsboro, OR (US); and Stephen R. Van Doren, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 28, 2022, as Appl. No. 17/955,353.
Application 17/955,353 is a continuation of application No. 17/187,271, filed on Feb. 26, 2021, granted, now 11,513,979.
Application 17/187,271 is a continuation of application No. 16/566,865, filed on Sep. 10, 2019, granted, now 10,970,238, issued on Apr. 6, 2021.
Claims priority of provisional application 62/836,288, filed on Apr. 19, 2019.
Prior Publication US 2023/0035420 A1, Feb. 2, 2023
Int. Cl. G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A device comprising:
an input/output (IO) interface to couple the device to a processor over a link;
a plurality of processing engines;
a plurality of work queues to store descriptors of work to be executed by a processing engine of the device; and
arbiter circuitry to dispatch descriptors in work queues to a processing engine; and
configuration registers comprising group configuration registers to store data that controls mapping of the processing engines and work queues into groups, each group comprising one or more work queues and one or more processing engines for processing descriptors in the work queues of the group.