US 12,332,812 B2
Memory device manageability bus
George Vergis, Portland, OR (US); and John R. Goles, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 9, 2021, as Appl. No. 17/470,278.
Prior Publication US 2021/0406206 A1, Dec. 30, 2021
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) 15 Claims
OG exemplary drawing
 
1. An electronic apparatus, comprising:
one or more substrates; and
a controller coupled to the one or more substrates, the controller including circuitry to:
enumerate a plurality of sideband addresses which are each to correspond to a different respective one of a plurality of memory devices, the plurality of sideband addresses each comprising a respective first portion and a respective second portion, wherein the circuitry to enumerate the plurality of sideband addresses comprises the circuitry to:
send an enumeration command to each of the plurality of memory devices;
assert first chip select signals which each correspond to a respective one of the plurality of memory devices; and
broadcast a value to each of the plurality of memory devices;
wherein, for each memory device of the plurality of memory devices:
a respective one of the first chip select signals is to enable the memory device to program the first portion of the corresponding sideband address based on the value and the enumeration command; and
the enumeration command is to cause the memory device to:
inject a respective current into a strap pin of the memory device;
convert a voltage value into a respective multi-bit digital value, wherein the voltage value is based on the respective current and a resistance value on the strap pin; and
set the second portion of the corresponding sideband address based on the respective multi-bit digital value; and
provide bi-directional communication with one of the plurality of memory devices based on the corresponding sideband address.