US 12,332,804 B2
Zone-aware memory management in memory sub-systems
Amit Bhardwaj, Hyderabad (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 8, 2024, as Appl. No. 18/629,470.
Application 18/629,470 is a continuation of application No. 18/094,744, filed on Jan. 9, 2023, granted, now 11,960,409.
Application 18/094,744 is a continuation of application No. 16/946,377, filed on Jun. 18, 2020, granted, now 11,550,727, issued on Jan. 10, 2023.
Prior Publication US 2024/0256463 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/10 (2016.01); G06F 12/02 (2006.01)
CPC G06F 12/10 (2013.01) [G06F 12/0253 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
responsive to receiving a request to store data referenced in association with a first zone of a logical address space of the memory device, storing the data in a memory block (MB), wherein the MB is selected in view of a version identifier of the first zone, the version identifier characterizing a number of times the first zone has been invalidated, and wherein invalidating the first zone comprises invalidating multiple logical block addresses (LBAs) of the first zone.