US 12,332,803 B2
Memory controller architecture
Emanuele Confalonieri, Segrate (IT); Stephen S. Pawlowski, Beaverton, OR (US); and Patrick Estep, Rowlett, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 26, 2023, as Appl. No. 18/202,802.
Claims priority of provisional application 63/357,562, filed on Jun. 30, 2022.
Prior Publication US 2024/0004799 A1, Jan. 4, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0897 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 11/1064 (2013.01); G06F 2212/1032 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory devices; and
a memory controller coupled to the plurality of memory devices via a plurality of memory channels;
wherein the plurality of memory channels are organized as a plurality of channel groups;
wherein the memory controller comprises a plurality of memory access request/response buffer sets, and wherein each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups; and
wherein the memory controller is configured to:
operate the plurality of channel groups as independent respective reliability, availability, and serviceability (RAS) channels; and
implement one of a chip kill error correction scheme and a RAID error recovery scheme on a per RAS channel basis.