US 12,332,802 B2
Multi-stage cache tag with first stage tag size reduction
Kermin ChoFleming, Hudson, MA (US); Yu Bai, Shrewsbury, MA (US); and Ping Zou, Westborough, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 21, 2021, as Appl. No. 17/352,628.
Prior Publication US 2022/0405209 A1, Dec. 22, 2022
Int. Cl. G06F 12/0895 (2016.01); G06F 12/02 (2006.01); G06F 12/0811 (2016.01); G06F 12/0853 (2016.01)
CPC G06F 12/0895 (2013.01) [G06F 12/0238 (2013.01); G06F 12/0811 (2013.01); G06F 12/0853 (2013.01); G06F 2212/1021 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a cache memory;
a primary tag memory;
a secondary tag memory; and
circuitry coupled to the cache memory, the primary tag memory, and the secondary tag memory to:
generate a cache tag for data to be stored in the cache memory,
store in the primary tag memory a primary tag which consists of only a subset of all bits of the cache tag, and
store in the secondary tag memory a secondary tag, wherein a combination of the primary tag and the secondary tag is equivalent to the cache tag, wherein a first size of the primary tag is smaller than a second size of the secondary tag.