| CPC G06F 12/0862 (2013.01) [G06F 12/08 (2013.01); G06N 3/0464 (2023.01); G06F 3/0673 (2013.01)] | 6 Claims |
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1. An processing device, comprising:
a first memory;
a memory management circuit, configured for reading an input data from a dynamic random access memory (DRAM), and storing the input data to the first memory;
a second memory; and
a convolution operation circuit configured for (i) reading the input data from the first memory, and (ii) performing a plurality of stages of calculations corresponding to a convolution operation to generate a plurality of output feature maps,
wherein after the convolution operation circuit performs a first-stage a calculation among the plurality of stages of calculations to generate at least one first data tile of a first output feature map among the plurality of output feature maps, the memory management circuit stores the at least one first data tile to the second memory; and
when a data amount of the at least one first data tile stored in the second memory satisfies a predetermined value, the memory management circuit transfers the at least one first data tile from the second memory to the first memory, and the convolution operation circuit reads the at least one first data tile from the first memory and accordingly performs a second stage calculation among the plurality of stages of calculations on the at least one first data tile to generate at least one second data tile of a second output feature map among the plurality of output feature maps, and stores the at least one second data tile to the second memory through the memory management circuit.
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