| CPC G06F 12/0835 (2013.01) [G06F 12/084 (2013.01); G06F 12/0891 (2013.01)] | 25 Claims |
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1. A processor, comprising:
a first cache;
interconnect circuitry to communicate with a second processor via a processor interconnect, wherein the second processor comprises a second cache;
processing circuitry to generate a memory read request for a corresponding memory address of a memory; and
cache controller circuitry to:
detect, based on the memory read request, a cache miss in the first cache, wherein the cache miss indicates that the first cache does not contain a valid copy of data for the corresponding memory address; and
request, based on the cache miss, the data from the second cache or the memory, wherein the second cache or the memory is selected for the request based on a current bandwidth utilization of the processor interconnect.
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