US 12,332,786 B2
Tracking memory modifications at cache line granularity
David Boles, Austin, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 8, 2024, as Appl. No. 18/629,269.
Application 18/629,269 is a continuation of application No. 17/744,332, filed on May 13, 2022, granted, now 11,989,126.
Prior Publication US 2024/0256449 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to:
receive a base address for a physical memory region;
receive a list of empty log memory buffers;
responsive to determining that a cache line in the physical memory region is in a modified state, store the cache line and metadata associated with the cache line in an active log memory buffer referenced by the list of empty log memory buffers; and
send a status message to a host processor, the status message comprising a session identifier of a logging session.