US 12,332,782 B2
Integrated circuit with address remapping circuitry to respond to a memory access request
Loris Luise, Ornago (IT); and Fabio Giuseppe De Ambroggi, Biassono (IT)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Mar. 22, 2023, as Appl. No. 18/188,365.
Prior Publication US 2024/0320148 A1, Sep. 26, 2024
Int. Cl. G06F 12/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 12/063 (2013.01) [G06F 13/1668 (2013.01); G06F 2212/254 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A device, comprising:
a CPU;
a bus;
a sub-system coupled to the bus;
address remapping circuitry coupled between the CPU and the bus; and
a system register coupled to the address remapping circuitry, wherein:
the CPU, in operation, provides a memory access request to the address remapping circuitry to access a memory of the sub-system via the bus,
the memory access request includes a requested memory address, wherein the address remapping circuitry, in operation, receives address matching data and address adjustment data from the system register,
the memory access request includes a data size, wherein the address remapping circuitry, in operation, provides the data size and an update address request to the system register, and
the system register, in operation, provides the address matching data and the address adjustment data to the address remapping circuitry in response to the update address request.