US 12,332,781 B2
Verification process for bit spreading error resistant memory system
Jeffrey E. Robertson, Ashburtn, VA (US)
Assigned to BAE Systems Information and Electronic Systems Integration Inc., Nashua, NH (US)
Filed by BAE SYSTEMS Information and Electronic Systems Integration Inc., Nashua, NH (US)
Filed on Sep. 19, 2023, as Appl. No. 18/470,111.
Prior Publication US 2025/0094342 A1, Mar. 20, 2025
Int. Cl. G06F 12/02 (2006.01); G06F 11/10 (2006.01)
CPC G06F 12/0292 (2013.01) [G06F 11/1044 (2013.01); G06F 2212/1008 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for verification of a design of a memory, the process comprising:
using a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAM s) of the memory;
writing data bits of a test data word to the physical address;
causing a design simulator to simulate a read from the logical address; and
comparing a result of the simulated read to the test data word to verify the design of the memory;
wherein the bit spreading geometry file is configured to specify a logical base address of the memory, a size of the memory, and a description of the each of the plurality of RAMs.