| CPC G06F 12/0246 (2013.01) [G06F 3/061 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 13/1673 (2013.01); G06F 2212/7203 (2013.01)] | 19 Claims |

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1. A data storage device comprising:
a memory;
an interface configured to communicate with a host comprising a plurality of host memory buffers; and
one or more processors configured to communicate with the memory and the interface, wherein the one or more processors are further configured to:
determine whether data should be stored in only one of the plurality of host memory buffers or in all of the plurality of host memory buffers, wherein it is determined that the data should be stored in all of the plurality of host memory buffers in response to determining that the data comprises a logical-to-physical address table related a frequently-accessed region; and
in response to determining that the data should be stored in all of the plurality of host memory buffers, store the data in all of the plurality of host memory buffers.
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