US 12,332,743 B2
Efficient memory use to support soft information in bit flipping decoders
Mustafa N. Kaynak, San Diego, CA (US); Eyal En Gad, Highland, CA (US); Zhengang Chen, San Jose, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Phong Sy Nguyen, Livermore, CA (US); and Dung V. Nguyen, San Jose, CA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 13, 2023, as Appl. No. 18/507,805.
Claims priority of provisional application 63/384,583, filed on Nov. 21, 2022.
Prior Publication US 2024/0168847 A1, May 23, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
performing a read operation of a first codeword including first hard data;
generating an error vector using a reliability metric of the first hard data;
storing the first hard data and the error vector in a first portion of a memory and a second portion of the memory;
returning a first corrected codeword that results from a combination of the error vector and the hard data from the first and second portions of memory;
performing a read operation of a second codeword including second hard data and soft information;
storing the second hard data and the soft information in the first portion of the memory and the second portion of the memory;
flipping a bit of the second hard data responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data stored in the first or second portions of memory; and
returning an updated second codeword that results from reading at least one of the first portion of the memory or the second portion of the memory.