US 12,332,741 B2
Memory controller performing error correction and operating method thereof
Jae Yong Son, Icheon (KR); Dae Sung Kim, Icheon (KR); and Min Su Choi, Icheon (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Jul. 10, 2023, as Appl. No. 18/349,712.
Claims priority of application No. 10-2022-0182284 (KR), filed on Dec. 22, 2022.
Prior Publication US 2024/0211345 A1, Jun. 27, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); H03M 13/11 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 11/141 (2013.01); H03M 13/1108 (2013.01); H03M 13/1177 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a read controller configured to sequentially perform a plurality of read retry operations on a memory device; and
an error correction circuit configured to perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and only perform a second error correction decoding, which has a higher performance than the first error correction decoding, after a last read retry operation among the plurality of read retry operations is completed, based on read data corresponding to a minimum USC value among the plurality of USC values.