| CPC G06F 11/1004 (2013.01) [G06F 11/0772 (2013.01); G06F 11/1068 (2013.01); G06F 11/3037 (2013.01); G06F 11/3041 (2013.01)] | 18 Claims |

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1. An apparatus, comprising:
a buffer semiconductor chip to be inserted between a memory channel disposed on a motherboard and a plurality of memory chips, the buffer semiconductor chip comprising:
a plurality of data strobe pins to propagate differential data strobe signal input/output (I/Os) to transport a plurality of data signals to corresponding data pins on the plurality of memory chips;
drive circuitry to redrive a received one of the differential data strobe signal I/Os to transport the plurality of data signals on a first data strobe pin of the plurality of data strobe pins to at least two sets of corresponding data pins on the plurality of memory chips;
a second data strobe pin of the plurality of data strobe pins repurposed to propagate a cyclic redundancy check (CRC) I/O to transport CRC information for the plurality of data signals, the CRC information to be transported on the second data strobe pin in parallel with the plurality of data signals transported on the first data strobe pin during a same burst transfer sequence; and
CRC logic circuitry to:
generate the CRC information from the plurality of data signals if the burst transfer sequence is a read, and
receive the CRC information and compare the CRC information to second CRC information generated from the plurality of data signals if the burst transfer sequence is a write.
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