US 12,332,738 B2
Memory computing integrated device and calibration method thereof
Bin Gao, Beijing (CN); Peng Yao, Beijing (CN); Huaqiang Wu, Beijing (CN); Jianshi Tang, Beijing (CN); and He Qian, Beijing (CN)
Assigned to TSINGHUA UNIVERSITY, Beijing (CN)
Appl. No. 18/574,247
Filed by TSINGHUA UNIVERSITY, Beijing (CN)
PCT Filed Dec. 13, 2021, PCT No. PCT/CN2021/137444
§ 371(c)(1), (2) Date Dec. 26, 2023,
PCT Pub. No. WO2023/000586, PCT Pub. Date Jan. 26, 2023.
Claims priority of application No. 202110823220.4 (CN), filed on Jul. 21, 2021.
Prior Publication US 2024/0320083 A1, Sep. 26, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/0793 (2013.01) [G06F 11/073 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A calibration method of a memory computing integrated device,
wherein the memory computing integrated device comprises a first processing element, the first processing element comprises a first calculation memristor array and a first calibration memristor array, and the first calculation memristor array is configured to receive a first calculation input data and calculate the first calculation input data to obtain a first output data; the first calibration memristor array is configured to receive a first calibration input data and calibrate the first output data according to the first calibration input data to obtain a first calibration output data; the first processing element is configured to output the first calibration output data,
the calibration method comprises:
determining a first calculation weight matrix corresponding to the first calculation memristor array through off-chip training, and writing the first calculation weight matrix into the first calculation memristor array;
based on the first calculation memristor array written with the first calculation weight matrix and the first calculation weight matrix, performing on-chip training on the first calibration memristor array to adjust a weight value of the first calibration memristor array.