US 12,332,733 B2
Determining an error handling mode
Cameron Mcnairy, Fort Collins, CO (US); and Michael Klinglesmith, Chambéry (FR)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on May 2, 2023, as Appl. No. 18/142,091.
Prior Publication US 2024/0370329 A1, Nov. 7, 2024
Int. Cl. G06F 11/07 (2006.01)
CPC G06F 11/079 (2013.01) [G06F 11/0745 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
first circuitry having a first interface; and
response circuitry configured to:
operate in accordance with an error handling mode selected from a plurality of error handling modes, the plurality of error handling modes comprising:
a first mode corresponding to no output containment,
a second mode corresponding to at least partial output containment, and
a third mode corresponding to providing a poison bit; and
receive an input selection that determines the error handling mode that is selected from the plurality of error handling modes and that is used to respond to an error associated with an output at the first interface.