US 12,332,732 B2
Pipelined hardware error classification and handling
Bryan Jason Wang, South Lake Tahoe, CA (US); and Samatha Gummalla, Dublin, CA (US)
Assigned to Cryptography Research, Inc., San Jose, CA (US)
Filed by Cryptography Research, Inc., San Jose, CA (US)
Filed on Dec. 8, 2022, as Appl. No. 18/077,943.
Claims priority of provisional application 63/290,343, filed on Dec. 16, 2021.
Prior Publication US 2023/0195553 A1, Jun. 22, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/0781 (2013.01) [G06F 11/073 (2013.01); G06F 11/0793 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A direct memory access (DMA) device comprising:
a hardware pipeline comprising a plurality of pipeline stages;
error detection logic to detect an error in the hardware pipeline; and
control logic to:
receive an indication of the error from the error detection logic;
classify the error in one of a plurality of categories based on a type of the error, a position of first data in a data stream that triggered the error, and a position of a pipeline stage in the hardware pipeline in which the error is detected; and
perform an error-response action based on the error classification of the error, wherein performing the error-response action comprises causing one or more of the plurality of pipeline stages to halt.