US 12,332,724 B2
Processing wakeup requests in a processing system having power management circuitry and a processing circuitry
Loic Hureau, Sainte Marie d'Attez (FR); Mohit Satsangi, New Delhi (IN); Ray Charles Marshall, Herts (GB); and Thomas Henry Luedeke, Oberbergkirchen (DE)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Oct. 3, 2023, as Appl. No. 18/480,116.
Claims priority of application No. 22306495 (EP), filed on Oct. 5, 2022.
Prior Publication US 2024/0118742 A1, Apr. 11, 2024
Int. Cl. G06F 1/00 (2006.01); G06F 1/3296 (2019.01)
CPC G06F 1/3296 (2013.01) 20 Claims
OG exemplary drawing
 
1. A processing system comprising:
power management circuitry comprising a handshake watchdog (HWD) timer, a first input, and a second input, wherein the power management circuitry is configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at the first input and a qualified wakeup request expected at the second input and configured to start the HWD timer counting in response to the initial wakeup request; and
processing circuitry coupled to the power management circuitry, the processing circuitry comprising:
a wakeup signal aggregator configured to receive wakeup signals from internal wakeup events and external wakeup events and configured to provide a notification of an occurrence of a wakeup event corresponding to any one of the received wakeup signals, wherein the notification is provided as the initial wakeup request to the power management circuitry; and
a low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and configured to provide the qualified wakeup request as a result of performing at least a portion of the low power mode exit sequence.