US 12,332,723 B2
Blocking latency events in multi-die architecture
Inder M. Sodhi, Palo Alto, CA (US); Achmed R. Zahir, Menlo Park, CA (US); Lior Zimet, Kerem Maharal (IL); Liran Fishel, Raanana (IL); Omri Flint, Ramat Hasharon (IL); and Ami Schwartzman, Kfar-Sava (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 12, 2024, as Appl. No. 18/438,665.
Application 18/438,665 is a continuation of application No. 17/933,168, filed on Sep. 19, 2022, granted, now 11,899,523.
Application 17/933,168 is a continuation of application No. 17/340,940, filed on Jun. 7, 2021, granted, now 11,467,655, issued on Oct. 11, 2022.
Prior Publication US 2024/0184355 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/3206 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3296 (2013.01) [G06F 1/3206 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a plurality of integrated circuit dies coupled together, wherein the plurality of integrated circuit dies include a first and a second integrated circuit die that include respective processor circuitry, wherein the second integrated circuit die is associated with a set of agent circuits;
wherein the first integrated circuit die is configured to:
detect a latency event to be performed that affects an availability of a memory associated with the plurality of integrated circuit dies;
determine read and write tolerance values for the latency event;
send the read and write tolerance values to the second integrated circuit die; and
block the latency event until at least an acknowledgment is received from the second integrated circuit die that the set of agent circuits is able to tolerate latencies corresponding to the read and write tolerance values.