US 12,332,722 B2
Latency reduction for transitions between active state and sleep state of an integrated circuit
Gia Tung Phan, Markham (CA); Randall Brown, Markham (CA); and Ashish Jain, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Mar. 24, 2023, as Appl. No. 18/189,993.
Prior Publication US 2024/0319781 A1, Sep. 26, 2024
Int. Cl. G06F 1/32 (2019.01); G06F 1/3228 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01)
CPC G06F 1/3275 (2013.01) [G06F 1/3228 (2013.01); G06F 1/3287 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A security processor comprising:
circuitry, wherein responsive to a first condition that indicates initialization of at least a first client of a plurality of clients of an integrated circuit, the circuitry is configured to:
initialize the first client using configuration information stored in a persistent on-chip memory that is accessible by the circuitry and inaccessible by the plurality of clients, responsive to an indication that the persistent on-chip memory stores valid information.