US 12,332,721 B2
Power supply control method
Gerald Briat, Vif (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Dec. 20, 2022, as Appl. No. 18/084,669.
Application 18/084,669 is a continuation of application No. 17/111,877, filed on Dec. 4, 2020, granted, now 11,567,558.
Claims priority of application No. 1913805 (FR), filed on Dec. 5, 2019.
Prior Publication US 2023/0129599 A1, Apr. 27, 2023
Int. Cl. G06F 1/3234 (2019.01); G06F 3/06 (2006.01); G11C 16/30 (2006.01)
CPC G06F 1/3275 (2013.01) [G06F 1/3243 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/30 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first memory chip including a first memory block and a second memory block;
wherein each of the first and second memory blocks is operable in a standby mode and an active mode;
a second memory chip separate from the first memory chip and including a state register configured to store a first mode control command signal for specifying standby or active mode for operation of the first memory block and further configured to store a second mode control command signal for specifying standby or active mode for operation of the second memory block;
a first latch having an input configured to receive the first mode control command signal, a clock input configured to receive a clock signal, and an output coupled to a mode control input of the first memory block;
a second latch having an input configured to receive the second mode control command signal, a clock input configured to receive said clock signal, and an output coupled to a mode control input of the second memory block; and
a processing circuit configured to generate said first and second mode control command signals for loading into the first and second registers, respectively.