US 12,332,720 B2
Low power optimization based upon host exit latency
Nissim Elmaleh, Meitar (IL); Amir Segev, Meiter (IL); and Shay Benisty, Beer Sheva (IL)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 6, 2023, as Appl. No. 18/218,864.
Claims priority of provisional application 63/453,288, filed on Mar. 20, 2023.
Prior Publication US 2024/0319779 A1, Sep. 26, 2024
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3268 (2013.01) [G06F 1/3296 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a wake up indication from a host device, wherein the data storage device is in a low power state;
receive a doorbell from the host device indicating that a new command is in a submission queue of the host device;
determine a host exit latency, wherein the host exit latency is a time between the wake up indication and the doorbell; and
utilize the host exit latency to select a group of actions from a plurality of group of actions based on the determining, wherein each of the plurality of group of actions comprises a different amount of low power state entrance actions to complete during a next low power state entrance.