US 12,332,711 B2
Systems and methods for mitigating peak current and improving overall performance
Srikar Karnam Venkat Naga, Bangalore (IN); Vandit Chauhan, Hyderabad (IN); Venkata Naga Satya Srinivas Nudurupati, Hyderabad (IN); Karimulla Syed, Bangalore (IN); Rohit Singh, Hyderabad (IN); Virat Deepak, San Diego, CA (US); Satyaki Mukherjee, Bangalore (IN); Ashok Kumar Immadi, Hyderabad (IN); and Ronald Alton, Oceanside, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
Filed on Apr. 7, 2023, as Appl. No. 18/297,246.
Claims priority of provisional application 63/492,131, filed on Mar. 24, 2023.
Prior Publication US 2024/0319773 A1, Sep. 26, 2024
Int. Cl. G06F 1/3206 (2019.01); G06F 1/26 (2006.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01)
CPC G06F 1/3206 (2013.01) [G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/3243 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method for performing peak current mitigation in an application program subsystem (APSS) comprising:
at boot time of the APSS, obtaining voltage and leakage current values of a power grid rail to which the APSS is electrically coupled;
using the obtained voltage and leakage current values to estimate a peak current value range of the APSS, where the estimated peak current value range of the APSS is determined from at least one equation (Eq. 1) comprising:

OG Complex Work Unit Math
where APSS_voltage (Volts) is the obtained voltage in Volts, Part leakage (mA) is the obtained leakage current in milliamps (mA), k1 is a first constant derived from a plot of peak current as a function of supply voltage and a ratio of actual leakage current to a leakage current obtained by modeling a system-on-chip (SoC) design, Design leakage estimate (mA) is the leakage current of a power grid in milliamps (mA) estimated using the model of the SoC design, and TH1 is a first threshold (TH) value also derived from the plot of peak current as a function of supply voltage and the ratio of actual leakage current to the leakage current obtained by using the model of the SoC design;
using a preconfigured estimated peak current value range-to-throttling level map to map the estimated peak current value range to a throttling level to be performed; and
at run time of the APSS, if conditions indicate that the APSS is operating at or near peak current, causing the mapped throttling level to be applied to at least one processor of the APSS.