US 12,332,710 B2
Techniques for testing PLP capacitors
Paul Abrahams, San Jose, CA (US); and Ilya Shlimenzon, San Jose, CA (US)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 2, 2020, as Appl. No. 16/919,443.
Application 16/919,443 is a continuation of application No. 15/703,664, filed on Sep. 13, 2017, granted, now 10,705,129.
Prior Publication US 2020/0393504 A1, Dec. 17, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H02J 7/00 (2006.01); G01R 21/00 (2006.01); G01R 27/26 (2006.01); G01R 31/30 (2006.01); G06F 1/30 (2006.01); G11C 5/14 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); H01G 11/12 (2013.01); G01R 31/64 (2020.01)
CPC G06F 1/30 (2013.01) [G01R 21/006 (2013.01); G01R 27/2688 (2013.01); G01R 31/3004 (2013.01); G06F 1/305 (2013.01); G11C 5/141 (2013.01); G11C 29/021 (2013.01); G11C 29/50 (2013.01); H01G 11/12 (2013.01); G01R 31/64 (2020.01)] 22 Claims
OG exemplary drawing
 
1. A memory storage device comprising:
a memory controller;
one or more non-volatile memory devices;
a volatile memory device; and
a power loss protection (PLP) device configured to supply a first voltage to the memory controller, the one or more non-volatile memory devices, and the volatile memory device in the event of a power loss or failure of the memory storage device, wherein
the PLP device is further configured to be increased from a first energy corresponding to the first voltage to a second energy prior to performing a test of a degradation of the PLP device.