CPC G06F 1/28 (2013.01) [G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 13/4273 (2013.01); G11C 5/063 (2013.01)] | 18 Claims |
1. A memory device comprising:
a plurality of integrated circuit memory dies arranged in a stack configuration, each memory die of the plurality of integrated circuit memory dies having an array of dynamic random access (DRAM) memory cells;
one or more command interfaces to receive commands associated with memory access to the memory cells of the plurality of integrated circuit memory dies; and
a sideband interface to receive mode signals that selectively transition the one or more command interfaces to a power state in which the one or more command interfaces do not respond to memory access commands.
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