US 12,332,683 B2
Synchronous reset deassertion circuit
Namit Varma, Karnataka (IN); Sarma Jonnavithula, Bangalore (IN); Mohan Krishna Vedam, Karantaka (IN); Christopher C. LaFrieda, Ridgefield, NJ (US); and Virantha N. Ekanayake, Baltimore, MD (US)
Assigned to Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed by Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed on Feb. 10, 2023, as Appl. No. 18/108,239.
Application 18/108,239 is a continuation of application No. 17/491,745, filed on Oct. 1, 2021, granted, now 11,681,324.
Prior Publication US 2023/0195162 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/12 (2006.01); G06F 1/24 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/24 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a counter block that:
receives a clock input and a counter reset input as inputs and generates a counter block signal as output; and
is configured to:
in response to the counter reset input being asserted, set the counter block signal to a first value; and
in response to the counter reset input being deasserted, set the counter block signal to a second value after a predetermined delay; and
a gating block that receives the clock input and a gating signal as inputs and generates a clock output as output, the clock output being set to the clock input while a first gating signal value is received and the clock output having a constant value while a second gating signal value is received.