CPC G06F 1/12 (2013.01) | 14 Claims |
1. A system for clock synchronization comprising:
a first processing unit operable at a first clock, wherein the first clock is provided by a system clock via a first variable delay;
a second processing unit operable at a second clock, wherein the second clock is provided by the system clock via a second variable delay; and
a sync line operably coupled between the first processing unit and the second processing unit, wherein:
the first processing unit is operable to send the first clock to the second processing unit via the sync line;
the second processing unit is operable to send the second clock to the first processing unit via the sync line;
the second processing unit is operable to generate a first phase difference between the first clock as received and the second clock;
the first processing unit is operable to generate a second phase difference between the second clock as received and the first clock;
the first variable delay is adjustable according to the first phase difference and the second phase difference; and
the second variable delay is adjustable according to the first phase difference and the second phase difference.
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