US 12,332,680 B2
Memory system related to clock synchronization
Kyu Dong Hwang, Icheon-si (KR); and Sang Sic Yoon, Icheon-si (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 9, 2023, as Appl. No. 18/107,914.
Claims priority of provisional application 63/314,128, filed on Feb. 25, 2022.
Claims priority of application No. 10-2022-0157256 (KR), filed on Nov. 22, 2022.
Prior Publication US 2023/0305592 A1, Sep. 28, 2023
Int. Cl. G11C 16/04 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G11C 7/22 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/12 (2013.01); G11C 7/222 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory controller configured to perform a memory access by providing a system clock signal, a data clock signal, and a chip selection signal; and
a memory device configured to communicate with the memory controller based on the system clock signal, the data clock signal, the chip selection signal, and the data clock enable signal,
wherein the memory controller is configured to provide a data clock enable signal to the memory device after the memory access.