US 12,332,679 B2
High output impedance current mirror circuit
Bo Sun, Carlsbad, CA (US); and Jafar Savoj, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 16, 2022, as Appl. No. 17/820,143.
Prior Publication US 2024/0061460 A1, Feb. 22, 2024
Int. Cl. G05F 3/26 (2006.01); H03K 19/0185 (2006.01); G05F 3/16 (2006.01)
CPC G05F 3/262 (2013.01) [G05F 3/26 (2013.01); H03K 19/018521 (2013.01); G05F 3/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a mirror stage circuit including a control node, wherein the mirror stage circuit is configured to generate a mirror current in an output node based on a reference current and a first voltage level of the control node; and
a feedback circuit configured to:
generate, using a voltage level of the output node, a scaled voltage level, wherein the scaled voltage level is generated based on a difference between transistors in the feedback circuit; and
generate, based on the scaled voltage level, a control current such that an increase in a value of the control current results in a decrease of the voltage level of the control node.