US 12,332,526 B2
Display substrate, display panel and display device
Xiaoye Ma, Beijing (CN); Yongxian Xie, Beijing (CN); Hui Guo, Beijing (CN); Jiale Li, Beijing (CN); Zhiwei Ding, Beijing (CN); Xiaowei Xu, Beijing (CN); Huanhuan Huang, Beijing (CN); and Ling Liu, Beijing (CN)
Assigned to Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Hefei Xinsheng Optoelectronics Technology Co., Ltd., Hefei (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Jul. 3, 2024, as Appl. No. 18/764,131.
Application 18/764,131 is a continuation of application No. PCT/CN2023/084483, filed on Mar. 28, 2023.
Prior Publication US 2024/0361657 A1, Oct. 31, 2024
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G06F 3/041 (2006.01); G06F 3/044 (2006.01); G09G 3/36 (2006.01)
CPC G02F 1/13629 (2021.01) [G02F 1/1368 (2013.01); G06F 3/0412 (2013.01); G06F 3/04164 (2019.05); G06F 3/0443 (2019.05); G09G 3/3614 (2013.01); G02F 2201/123 (2013.01); G06F 2203/04103 (2013.01); G09G 2300/0426 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0257 (2013.01); G09G 2330/023 (2013.01); G09G 2354/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate;
a plurality of gate-line groups, on a side of the base substrate and extending along a first direction, wherein at least one of the plurality of gate-line groups comprises two gate lines extending along the first direction;
a plurality of data lines, on the side of the base substrate with the gate lines and extending in a second direction; wherein the plurality of data lines comprise first type of data lines and second type of data lines alternately arranged along the first direction;
a plurality of transistors, in an area formed by an intersection of the gate-line groups and the data lines, wherein the plurality of transistors comprise: sub-transistor groups arranged between adjacent gate-line groups and arranged along the first direction, each of the sub-transistor groups comprises two transistors, the transistors in a same sub-transistor group are connected with a same gate line, the transistors in adjacent sub-transistor groups are connected with different gate lines, and the transistors in a same sub-transistor group are connected with different data lines;
a plurality of pins, on the side of the base substrate with the gate lines, wherein the plurality of pins comprise: first type of pins and second type of pins alternately arranged along the first direction; two adjacent first type of data lines are connected with a same first type of pin, and adjacent second type of data lines are connected with a same second type of pin.