US 12,332,525 B2
Array substrate and display panel
Youhuang Lin, Guangdong (CN); and Zhiming Zhan, Guangdong (CN)
Assigned to TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
Appl. No. 17/611,521
Filed by TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Oct. 12, 2021, PCT No. PCT/CN2021/123267
§ 371(c)(1), (2) Date Apr. 6, 2023,
PCT Pub. No. WO2023/050471, PCT Pub. Date Apr. 6, 2023.
Claims priority of application No. 202111152323.9 (CN), filed on Sep. 29, 2021.
Prior Publication US 2024/0045288 A1, Feb. 8, 2024
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/133514 (2013.01); G02F 1/134345 (2021.01); G02F 1/13624 (2013.01); G02F 1/1368 (2013.01); G02F 2201/124 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a display area and a non-display area surrounding the display area;
a plurality of pixels disposed in the display area, wherein each of the pixels comprises a first sub-pixel and a second sub-pixel arranged along a column direction, the plurality of pixels comprise a plurality of pixel rows and a plurality of pixel columns, in each of the pixel rows, a first sub-pixel row and an adjacent second sub-pixel row are separated by a first interval, and two adjacent pixel rows are separated by a second interval;
a plurality of data lines extending along the column direction and connected to the plurality of pixel columns;
a plurality of gate lines extending along a row direction and connected to the plurality of pixel rows, wherein each of the gate lines is disposed in a corresponding first interval;
a plurality of shared electrode lines extending along the row direction, wherein each of the shared electrode lines is disposed in a corresponding first interval and is adjacent to a corresponding gate line;
a plurality of common electrode lines, wherein each of the common electrode lines is disposed between two adjacent first intervals, each of the common electrode lines comprises a main electrode and a plurality of comb-shaped electrodes, the main electrode extends along the row direction and disposed in a corresponding second interval, and the plurality of comb-shaped electrodes extend along the column direction and extend toward at least one adjacent first interval;
a shared electrode bus line extending along the column direction, disposed in the non-display area, and connected to the plurality of shared electrode lines; and
a common electrode bus line extending along the column direction, disposed in the non-display area, and connected to each of the main electrodes,
wherein in one of the pixels, the pixel comprises a shared thin film transistor, the first sub-pixel comprises a first thin film transistor and a first pixel electrode, and the second sub-pixel comprises a second thin film transistor and a second pixel electrode;
gates of the shared thin film transistor, the first thin film transistor, and the second thin film transistor are connected to a same gate line;
sources of the first thin film transistor and the second thin film transistor are connected to a same data line;
a drain of the first thin film transistor is connected to the first pixel electrode via a first through hole, and a drain of the second thin film transistor is connected to the second pixel electrode via a second through hole;
a drain of the shared thin film transistor is connected to the drain of the second thin film transistor, a source of the shared thin film transistor is connected to one of the shared electrode lines via a third through hole, and the gate line and the shared electrode line respectively connected to the gate and the source of the shared thin film transistor are disposed in a same first interval; and
wherein the first through hole, the second through hole, and the third through hole all are disposed corresponding to the shared electrode line.