US 12,332,521 B2
Display panel and manufacturing method thereof
Liang Li, Huizhou (CN)
Assigned to HUIZHOU CHINA STAR OPTOELECTRONICS DISPLAY CO., LTD., Huizhou (CN); and TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/440,722
Filed by HUIZHOU CHINA STAR OPTOELECTRONICS DISPLAY CO., LTD., Huizhou (CN); and TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
PCT Filed Aug. 10, 2021, PCT No. PCT/CN2021/111664
§ 371(c)(1), (2) Date Nov. 15, 2021,
PCT Pub. No. WO2023/010589, PCT Pub. Date Feb. 9, 2023.
Claims priority of application No. 202110880621.3 (CN), filed on Aug. 2, 2021.
Prior Publication US 2024/0027838 A1, Jan. 25, 2024
Int. Cl. G02F 1/1339 (2006.01); G02F 1/1333 (2006.01); G02F 1/1335 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/1339 (2013.01) [G02F 1/133368 (2021.01); G02F 1/133512 (2013.01); G02F 1/136295 (2021.01); G02F 2201/121 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A display panel, having an active area and a seal area arranged around the active area and including:
a first substrate, having a signal trace and an insulating protection layer, and the signal trace is positioned in the seal area, and the insulation protection layer covers the signal trace, and the insulation protection layer has an opening, and the opening exposes the signal trace;
a second substrate, oppositely arranged with the first substrate, and the second substrate has a common electrode; and
a seal, positioned between the first substrate and the second substrate, and the seal covers the signal trace, the seal is doped with a conductor, and the conductor conducts the signal trace and the common electrode at the opening;
wherein a portion of the insulating protection layer located in the active area has a first thickness, and a portion of the insulating protection layer located in the seal area has a second thickness, and the first thickness is greater than the second thickness;
wherein the first substrate further includes an array substrate-side common electrode, and the array substrate-side common electrode is located in the seal area, and the array substrate-side common electrode and the signal trace are arranged in a same layer and spaced apart;
wherein the insulating protection layer includes an organic film layer, and the opening includes a first opening, and the first opening is disposed corresponding to the signal trace and penetrates the organic film layer;
the organic film layer includes a first portion and a second portion, and the first portion is located in the active area, and the second portion is located in the seal area, and a thickness of the first portion is greater than a thickness of the second portion;
wherein the insulating protection layer further includes a passivation layer disposed on a side of the organic film layer close to the signal trace, and the passivation layer is located in the active area and the seal area, and the first opening penetrates the passivation layer;
wherein the insulating protection layer further includes a gate insulating layer, and the first substrate further includes a transparent conductive layer;
the gate insulating layer is located on a side of the passivation layer close to the signal trace, and the opening further includes a second opening being located in the gate insulating layer and penetrating the gate insulating layer, and the second opening corresponds to and communicates with the first opening, and the transparent conductive layer is entirely located in the second opening, and the conductor is connected to the signal trace through the transparent conductive layer.