US 12,332,309 B2
Built-in self-test for network on chip fabric
Dawn Maxon, San Jose, CA (US); Eric A. Norige, Santa Clara, CA (US); Joji Philip, San Jose, CA (US); William John Bainbridge, Palo Alto, CA (US); and Joseph B. Rowlands, Alviso, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 11, 2021, as Appl. No. 17/399,942.
Prior Publication US 2021/0373075 A1, Dec. 2, 2021
Int. Cl. G01R 31/28 (2006.01); G01R 31/3187 (2006.01)
CPC G01R 31/3187 (2013.01) [G01R 31/2856 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a network-on-chip (NOC) fabric comprising a plurality of routes to communicate data between a plurality of agents;
a plurality of built-in self-test (BIST) generators, wherein a BIST generator of the plurality of BIST generators is coupled between an agent of the plurality of agents and the NOC fabric and is to transmit at least one test pattern through the NOC fabric, wherein the BIST generator is to arbitrate, for transmission to the NOC fabric, between packets sent by the agent and packets generated by the BIST generator; and
a plurality of BIST checkers, wherein a BIST checker of the plurality of BIST checkers is coupled between the agent of the plurality of agents and the NOC fabric and is to receive at least one test pattern through the NOC fabric from at least one of the plurality of BIST generators and to verify whether the at least one test pattern was transmitted correctly through the NOC fabric.