US 12,332,308 B2
Processing devices for reducing scan traffic, method and computer program
Min Liu, Portland, OR (US); Jaemon Franko, Gig Harbor, WA (US); Xia Jin, Shanghai (CN); Xiang Li, Shanghai (CN); Jiaqi Liu, Shanghai (CN); and Krishna Surya, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 18/551,879
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Jun. 25, 2021, PCT No. PCT/CN2021/102560
§ 371(c)(1), (2) Date Sep. 22, 2023,
PCT Pub. No. WO2022/267065, PCT Pub. Date Dec. 29, 2022.
Prior Publication US 2024/0159829 A1, May 16, 2024
Int. Cl. G01R 31/3185 (2006.01)
CPC G01R 31/318591 (2013.01) [G01R 31/31853 (2013.01); G01R 31/318547 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing device for reducing scan traffic, comprising:
one or more interfaces configured to transmit information to at least one register access interface; and
processing circuitry configured to control the one or more interfaces and to:
obtain register parameters of a plurality of registers of at least one functional unit of a processing unit, wherein the register parameters include information needed to request an access to the plurality of registers in the at least one functional unit of the processing unit; and
generate a bulk register access based on the register parameters to access the plurality of registers of the at least one functional unit.