| CPC G01R 31/31727 (2013.01) [G01R 31/31726 (2013.01); G01R 31/31926 (2013.01)] | 20 Claims |
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1. A transmitter comprising:
a pattern generator configured to generate test data having a predetermined pattern;
a data generator configured to receive the generated test data and a data signal, generate retimed test data and a retimed data signal by adjusting a delay amount of each of the test data and the data signal based on adjusted clock signals;
a serializer configured to generate a serial data signal by serializing the retimed data signal based on multi-phase clock signals;
a transmission driver configured to generate an output data signal based on the serial data signal and transmit the output data signal through a channel; and
a feedback circuit configured to detect a setup margin and a hold margin of the retimed test data through a separate path different from a path of the retimed data signal, and configured to generate the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and the detected hold margin of the retimed test data,
wherein the feedback circuit comprises:
at least one dummy multiplexer configured to provide at least one output signal by sequentially selecting at least one portion from among test bits of the retimed test data based on the multi-phase clock signals;
a detection circuit configured to detect the setup margin and the hold margin of the retimed test data based on the at least one output signal and a strobe signal selected from among test bits of the test data, and configured to generate a detection signal indicating the detected setup margin and the detected hold margin of the retimed test data; and
a clock timing adjuster configured to generate the adjusted clock signals by adjusting the delay amounts of the multi-phase clock signals based on the detection signal.
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