US 12,332,304 B1
System and method for automatic fault detection in an electronic design
Sushobhit Singh, Uttar Pradesh (IN); Arvind Nembili Veeravalli, Karnataka (IN); Naresh Kumar, Uttar Pradesh (IN); Mahesh D. Sadhankar, Uttar Pradesh (IN); and Daksh Bakshi, Haryana (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Aug. 29, 2022, as Appl. No. 17/897,360.
Int. Cl. G01R 31/317 (2006.01)
CPC G01R 31/31725 (2013.01) 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for automatic fault detection during a timing analysis comprising:
reading, using a processor, design and power intent information associated with an electronic design;
automatically identifying a plurality of inter-power domain paths from the design and power intent information;
automatically filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach, wherein identifying the one or more faulty inter-power domain paths reduces a search space; and
automatically generating a report depicting the one or more faulty inter-power domain paths.