US 12,332,301 B2
Measuring device defect sensitization in transistor-level circuits
Mayukh Bhattacharya, Palo Alto, CA (US); Jonti Talukdar, Durham, NC (US); Shan Yuan, San Jose, CA (US); and Huiping Huang, San Jose, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Nov. 29, 2022, as Appl. No. 18/071,080.
Claims priority of provisional application 63/398,424, filed on Aug. 16, 2022.
Prior Publication US 2024/0061035 A1, Feb. 22, 2024
Int. Cl. G01R 31/28 (2006.01); G06F 30/323 (2020.01); G06F 30/3308 (2020.01)
CPC G01R 31/2848 (2013.01) [G06F 30/323 (2020.01); G06F 30/3308 (2020.01)] 8 Claims
OG exemplary drawing
 
1. A method of determining defect sensitization, the method comprising:
parsing a netlist of a circuit design to determine a plurality of potential defects;
partitioning the circuit design into a plurality of blocks;
generating, based on the plurality of blocks, a graph representing the circuit design;
determining a transitive closure of the graph indicating reachability relationships among the plurality of blocks;
grouping the plurality of potential defects based on the reachability relationships among the plurality of blocks indicated by the transitive closure of the graph to produce a plurality of groups of potential defects;
selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects;
simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks; and
determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.