US 12,332,298 B2
Semiconductor test device and system and test method using the same
Meehyun Lim, Seoul (KR); Sungyeol Kim, Yongin-si (KR); Hyungjung Yong, Seongnam-si (KR); and Jinyeong Yun, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 31, 2023, as Appl. No. 18/240,957.
Application 18/240,957 is a continuation of application No. 16/924,971, filed on Jul. 9, 2020, granted, now 11,782,085.
Claims priority of application No. 10-2019-0153606 (KR), filed on Nov. 26, 2019.
Prior Publication US 2023/0408574 A1, Dec. 21, 2023
Int. Cl. G01R 31/28 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC G01R 31/2803 (2013.01) [G01R 31/2815 (2013.01); H01L 24/14 (2013.01); H01L 25/0657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for testing a semiconductor package including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, the method comprising:
controlling a test circuit included in the first semiconductor chip of the semiconductor package to cause emission of an electric field from at least a set of first upper pads among first upper pads of the second semiconductor chip;
detecting an electric field emitted from the set of first upper pads using a sensor disposed above upper surfaces of the first upper pads and spaced apart therefrom by a predetermined interval;
outputting a signal from the sensor, the signal including information about an electrical field waveform; and
determining a contact failure between the first semiconductor chip and the second semiconductor chip in a signal processing device using the signal output from the sensor.