US 12,332,283 B2
Voltage-variation detection under clock fluctuations
Emre Tuncer, Santa Cruz, CA (US); Huachang Xu, Mountain View, CA (US); Ramprasad Raghavan, Sunnyvale, CA (US); Fanny Gur, Los Gatos, CA (US); and Manish Harnur, Sunnyvale, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Oct. 31, 2022, as Appl. No. 18/051,442.
Application 18/051,442 is a continuation of application No. 16/936,169, filed on Jul. 22, 2020, granted, now 11,486,911.
Application 16/936,169 is a continuation of application No. PCT/US2019/062282, filed on Nov. 19, 2019.
Prior Publication US 2023/0131119 A1, Apr. 27, 2023
Int. Cl. G01R 19/165 (2006.01); G06F 1/10 (2006.01); G06F 21/75 (2013.01); H03K 5/00 (2006.01)
CPC G01R 19/16533 (2013.01) [G06F 1/10 (2013.01); G06F 21/755 (2017.08); H03K 5/00 (2013.01); H03K 2005/00019 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a clock generator configured to generate a clock signal with one or more frequency fluctuations;
a clock line coupled to the clock generator and configured to propagate the clock signal with the one or more frequency fluctuations;
a first voltage-dependent circuit coupled to the clock line, the first voltage-dependent circuit configured to produce a first signal that is indicative of a voltage level responsive to the clock signal and based on a first voltage sensitivity, the first voltage-dependent circuit comprising:
a delay circuit coupled to the clock line and configured to delay the clock signal to produce a delayed clock signal, the delay circuit configured to provide a programmable delay amount to delay the clock signal and produce the delayed clock signal, the delay circuit comprising:
multiple delay units coupled together in series; and
at least one multiplexer including at least one control input; and
a sample circuit coupled between the delay circuit and a voltage analysis circuit, the sample circuit configured to sample the delayed clock signal to produce the first signal;
a second voltage-dependent circuit coupled to the clock line, the second voltage-dependent circuit configured to produce a second signal that is indicative of the voltage level responsive to the clock signal and based on a second voltage sensitivity; and
the voltage analysis circuit coupled to the first voltage-dependent circuit and the second voltage-dependent circuit, the voltage analysis circuit configured to:
detect a voltage-based attack by neutralizing the one or more frequency fluctuations of the clock signal based on a combination of the first signal and the second signal; and
generate a voltage alert signal based on detection of the voltage-based attack.