US 12,332,126 B2
Low-power-consumption low-voltage digital temperature sensor
Zhikuang Cai, Nanjing (CN); Zixuan Wang, Nanjing (CN); Chen Li, Nanjing (CN); Zushuai Xie, Nanjing (CN); Jingjing Guo, Nanjing (CN); Lu Liu, Nanjing (CN); and Yufeng Guo, Nanjing (CN)
Assigned to Nanjing University Of Post And Telecommunications, Jiangsu (CN)
Appl. No. 18/264,069
Filed by Nanjing University Of Post And Telecommunications, Nanjing (CN)
PCT Filed Mar. 22, 2021, PCT No. PCT/CN2021/077539
§ 371(c)(1), (2) Date Aug. 2, 2023,
PCT Pub. No. WO2022/116400, PCT Pub. Date Jun. 9, 2022.
Claims priority of application No. 202011394619.7 (CN), filed on Dec. 3, 2020.
Prior Publication US 2024/0310220 A1, Sep. 19, 2024
Int. Cl. G01K 7/01 (2006.01)
CPC G01K 7/01 (2013.01) 3 Claims
OG exemplary drawing
 
1. A low-power-consumption low-voltage digital temperature sensor, characterized in that: comprising a first ring oscillator, a second ring oscillator, a first integrator, a second integrator, a D trigger and a linear optimization module, wherein an output end of the first ring oscillator is connected with an input end of the first integrator; an output end of the second ring oscillator is connected with a clock input end of the second integrator, a clock input end of a state machine and a clock input end of the D trigger; an output end of the first integrator is connected with a data input end of the D trigger; an output end of the second integrator is connected with a data input end of the state machine; a first output end of the state machine is connected with a control end of the first integrator; a second output end of the state machine is connected with a control end of the second integrator; and a data output end of the D trigger is connected with an input end of the linear optimization module; the first ring oscillator comprises N first delay units, wherein N is a positive odd number, the N first delay units are sequentially connected end to end form a closed loop, and an output end of a last first delay unit is used as an output end of the first ring oscillator; the first delay unit comprises a first PMOS tube [MP1], a second PMOS transistor [MP2], a first NMOS transistor [MN1] and a first metal-oxide semiconductor (MOS) capacitor [CM1], wherein, a gate of the first PMOS transistor [MP1] is connected with a gate of the first NMOS transistor [MN1] and used as an input end of the first delay unit; a drain of the first PMOS transistor [MP1] is connected with a drain of the first NMOS transistor [MN1], a source of the second PMOS transistor [MP2] and a drain second PMOS transistor a substrate of the second PMOS transistor [MP2] an upper electrode plate of first MOS capacitor [CM1] and used as an output end of the first delay unit; a source of the first PMOS transistor [MP1] and a gate of the second PMOS transistor [MP2] are connected with power supply voltage; a source of the first NMOS transistor [MN1] and a lower electrode plate of the first MOS capacitor [CM1] are connected to ground.