US RE50,010 E1
Clock gating circuit
Ah-Reum Kim, Daegu (KR); Hyun Lee, Incheon (KR); and Min-su Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 15, 2022, as Appl. No. 17/672,371.
Application 17/672,371 is a division of application No. 15/139,949, filed on Apr. 27, 2016, granted, now 10,230,373, issued on Mar. 12, 2019.
Application 17/672,371 is a reissue of application No. 16/259,631, filed on Jan. 28, 2019, granted, now 10,566,977, issued on Feb. 18, 2020.
Claims priority of application No. 10-2015-0058762 (KR), filed on Apr. 27, 2015; and application No. 10-2015-0139061 (KR), filed on Oct. 2, 2015.
Int. Cl. H03K 3/356 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 19/01855 (2013.01) [H03K 3/012 (2013.01); H03K 3/037 (2013.01); H03K 3/356104 (2013.01); H03K 3/356191 (2013.01); H03K 19/0013 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor circuit comprising:
an input circuit configured to determine a voltage level of a first node;
a first circuit configured to propagate a value of the first node to a second node based on a voltage level of a clock signal;
a second circuit configured to propagate a value of the second node to a third node [ and determine a value of the third node ] based on the voltage level of the clock signal;
a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal; and [ second node and the voltage level of the clock signal; and ]
an output circuit configured to determine a voltage level of a fourth node based on a voltage level of the third node,
wherein the first circuit includes a first transistor gated to the voltage level of the first node, a second transistor gated to the voltage level of the third node, and a third transistor gated to the voltage level of the of the clock signal,
[ wherein the first transistor is connected with the second transistor in series,
wherein one of a source or a drain of the first transistor is connected to an input from the first node, and ]
wherein the second circuit includes [ an inverter inverting the second node, ] a fourth transistor gated to the voltage level of the clock signal, and
wherein a source terminal of the first transistor is connected to an input from the first node [ output of the inverter, and a fifth transistor gated to the clock signal and connected with the fourth transistor] .