	US 12,010,854 B1
	Multi-level hydrogen barrier layers for memory applications and methods of fabrication
Noriyuki Sato, Hillsboro, OR (US); Niloy Mukherjee, San Ramon, CA (US); Mauricio Manfrini, Heverlee (BE); Tanay Gosavi, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Somilkumar J. Rathi, San Jose, CA (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 16, 2021, as Appl. No. 17/553,480.
Application 17/553,480 is a continuation of application No. 17/550,904, filed on Dec. 14, 2021.
Int. Cl. H01L 21/00 (2006.01); H10B 53/30 (2023.01)

CPC H10B 53/30 (2023.02)

20 Claims

1. A method of fabricating a device structure, the method comprising:

forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region;

depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect;

forming an electrode structure on the first conductive interconnect by a first process comprising:

etching a first opening in the etch stop layer;

depositing a first conductive hydrogen barrier layer in the first opening; and

depositing a first conductive material on the first conductive hydrogen barrier layer;

forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack;

depositing a second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer;

forming a via electrode on the memory device by a second process comprising:

forming a second opening in the second dielectric;

depositing a second conductive hydrogen barrier layer on at least a portion of a first uppermost surface of the memory device in the second opening; and

depositing a second conductive material on the second conductive hydrogen barrier layer;

etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material;

etching the third dielectric to form a via opening and exposing the second conductive interconnect;

filling the via opening with a first one or more conductive materials;

planarizing to form a via structure;

depositing a fourth dielectric on the via electrode, on the second dielectric, on the third dielectric and on the via structure;

forming a contact electrode by a third process, comprising:

forming a third opening in the fourth dielectric and exposing the via electrode;

depositing a third conductive hydrogen barrier layer on the via electrode in the third opening;

depositing a second one or more conductive materials on the third conductive hydrogen barrier layer; and

planarizing the second one or more conductive materials and the third conductive hydrogen barrier layer;

forming a trench opening in the fourth dielectric and exposing the via structure; and

depositing a third one or more conductive materials in the trench opening on the via structure to form a metal line.