| CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate;
a peripheral circuit including a plurality of transistors disposed on the substrate; and
a memory cell array controlled by the peripheral circuit,
wherein each of the plurality of transistors includes:
an isolation region disposed on the substrate;
an active region disposed in the isolation region;
a gate extending in a second direction on the active region; and
source and drain regions respectively extending in a first direction perpendicular to the second direction in the active region on first and second sides of the gate,
wherein the source and drain regions include:
low-concentration source and drain doping regions including first low-concentration source and drain doping regions disposed in a gate-adjacent region adjacent to the gate and second low-concentration source and drain doping regions disposed in a gate-distant region separated from the gate by the gate-adjacent region; and
high-concentration source and drain doping regions respectively disposed in the low-concentration source and drain doping regions and having higher doping concentrations than the low-concentration source and drain doping regions, and
wherein a first length in the second direction of the first low-concentration source and drain doping regions is greater than a second length in the second direction of the second low-concentration source and drain doping regions.
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