US 12,010,835 B2
Three-dimensional memory device with a conductive drain-select-level spacer and methods for forming the same
Zhixin Cui, Nagoya (JP); and Satoshi Shimizu, Yokkaichi (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Apr. 27, 2021, as Appl. No. 17/241,321.
Prior Publication US 2022/0344362 A1, Oct. 27, 2022
Int. Cl. H10B 41/27 (2023.01); G11C 8/14 (2006.01); H10B 41/10 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 8/14 (2013.01); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 2 Claims
OG exemplary drawing
 
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers, wherein the electrically conductive layers comprise word-line-level electrically conductive layers and drain-select-level electrically conductive layers located above the word-line-level electrically conductive layers;
a first backside trench fill structure extending along a first horizontal direction and comprising a first dielectric surface that contacts first sidewalls of each layer within the alternating stack;
a second backside trench fill structure extending along the first horizontal direction, separated from the first backside trench fill structure along a second horizontal direction perpendicular to the first horizontal direction, and comprising a second dielectric surface that contacts second sidewalls of each layer within the alternating stack;
a contact-level dielectric layer overlying the alternating stack;
drain-select-level isolation structures extending through the contact-level dielectric layer and the drain-select-level electrically conductive layers but not through the word-line-level electrically conductive layers of the alternating stack, wherein the drain-select-level isolation structures extend in the first horizontal direction and are spaced apart along the second horizontal direction;
memory opening fill structures vertically extending through the alternating stack in a memory array region in which each layer within the alternating stack is present, wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a memory film, wherein an entirety of the memory opening fill structures underlies a bottom surface of the contact-level dielectric layer;
an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers to a second drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers, wherein the electrically conductive spacer extends along the second horizontal direction and contacts ends of the first and the second drain-select-level electrically conductive layers along the second horizontal direction; and
an additional electrically conductive spacer extending vertically and electrically connecting a third drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers to a fourth drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers.