US 12,010,449 B2
Imaging devices with gated time-of-flight pixels with fast charge transfer
Frederick Brady, Webster, NY (US); Adarsh Basavalingappa, Fairport, NY (US); Taisuke Suwa, Auderghem (BE); Michiel Timmermans, Werchter (BE); and Sungin Hwang, Pittsford, NY (US)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/610,257
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed May 21, 2020, PCT No. PCT/IB2020/000398
§ 371(c)(1), (2) Date Nov. 10, 2021,
PCT Pub. No. WO2020/234648, PCT Pub. Date Nov. 26, 2020.
Claims priority of provisional application 62/850,911, filed on May 21, 2019.
Prior Publication US 2022/0247952 A1, Aug. 4, 2022
Int. Cl. H04N 25/76 (2023.01); G01S 7/4863 (2020.01); G01S 17/894 (2020.01); H01L 27/146 (2006.01)
CPC H04N 25/76 (2023.01) [G01S 7/4863 (2013.01); G01S 17/894 (2020.01); H01L 27/14607 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a pixel array including a plurality of pixels, each pixel including:
a photoelectric conversion region that converts incident light into electric charge; and
a charge transfer section coupled to the photoelectric conversion region and having line symmetry along a first axis that passes through the charge transfer section in a plan view, the charge transfer section including:
a first transfer transistor coupled to a first floating diffusion and the photoelectric conversion region and located within a first half of the pixel in the plan view;
a second transfer transistor coupled to a second floating diffusion and the photoelectric conversion region and located within the first half of the pixel in the plan view; and
a third transfer transistor coupled to the photoelectric conversion region and an overflow region and located within the first half of the pixel between the first transfer transistor and the second transfer transistor in the plan view.